The present invention relates to interface devices generally and, more particularly, to an interface device in an intelligent input/output system.
An intelligent input/output system is defined by the Intelligent I/O (I2O) Architecture Specification, version 1.5, dated March 1997, and the Intelligent I/O (I2O) Architecture Specification, version 2.0, dated March 1999, the relevant portions of each which are hereby incorporated by reference. FIG. 1 shows a circuit 10 implementing such an architecture. The circuit 10 is shown having a messaging unit (including four FIFO control logic blocks 12, 14, 16 and 18), a shared memory 20 to store message frames, an interrupt block 22, a first system interface bus 24, a local bus interface bus 26 and a local processor 28. The structure of the circuit 10 is described in the I2O Architecture Specification on pages 4-2 through 4-7. The circuit 10 illustrates the typical structure of an I2O messaging unit. In current solutions, the logic is distributed among up to three distinct elements connecting two buses of two different clock domains. The three elements are a processing component, a random access memory component, and a bus interface component. The circuit 10 suffers from several problems including (i) increased design complexity, (ii) increased manufacturing complexity, and (iii) decreased overall performance.
The present invention concerns a circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.
The objects, features and advantages of the present invention include providing a messaging unit that may be used in an I2O system that may (i) optimize messaging functions, (ii) minimize circuit card complexity, (iii) increase performance of the I2O message passing protocol, (iv) minimize component and manufacturing costs, (v) allow simultaneous access to the messaging unit by two buses, (vi) allow simultaneous access to a message frames storage device and the message queue storage device, (vii) place the message unit storage device in a central arbitrated area having a single clock domain, (viii) allow operation of a first and second bus having an independent clock domain, and/or (ix) implement the messaging unit as a self contained, single chip solution implementing all hardware required for an I2O compliant messaging unit.